The present invention relates to a logic circuit module having excellent area efficiency and capable of representing a large number of logics, a method for designing a semiconductor integrated circuit using such a logic circuit module, and a semiconductor integrated circuit.
In an FPGA (Field Programmable Gate Array), a device is first manufactured in such a form that can be used for general purposes, so that a desired circuit operation is implemented by writing data to storage elements incorporated in advance into the device or blowing fuses.
In general, a gate array is produced in advance up to a transistor portion, so that a desired circuit operation is implemented using all wiring layers. However, there is also a short-term gate array in order to implement a desired circuit in a shorter period. In the short-term gate array, not all of the wiring layers are produced in advance. Instead, some of the wiring layers are produced in advance, so that a desired circuit is formed using only the remaining wiring layers.
Moreover, in a cell base IC (Integrated Circuit), correction macro cells are incorporated in advance in order to quickly handle any erroneous circuit design found in the manufactured cell base IC. Thus, when the necessity for correction arises, only the wiring layers are corrected using the correction macro cells.
Such an FPGA and short-term gate array have a small amount of individually modifiable wiring resources for forming a semiconductor integrated circuit implementing a desired operation. Therefore, not a small unit like a transistor but a logic module capable of implementing a large number of logics by a single unit is used as a base unit for implementing a logic, in order to reduce the amount of individually modifiable wirings. A method for designing a semiconductor integrated circuit in such a conventional FPGA and short-term gate array will now be described in connection with FIGS. 16A and 16B. Conventionally, as shown in FIG. 16A, a multiplicity of 4-1 multiplexers M13 are used as logic circuit modules in order to form a logic circuit in such a form that can be used for general purposes. Each input terminal of the logic circuit module M13 is connected to a power supply, ground or external wiring, thereby expressing a plurality of types of logic circuits. FIG. 16B shows an example of a NAND logic implemented with the logic circuit module M13. In FIG. 16B, input terminals TI1311, TI1312 and TI1313 are connected to a power supply, an input terminal TI1314 is grounded, and input terminals TI1315 and TI1316 are respectively connected to external input terminals A13 and A14. An output terminal TO1311 is connected to an external output terminal Y13. Thus, a NAND output of the external input terminals A13 and A14 is output to the external output terminal Y13.
A conventional implementation method in which macro cells are incorporated in advance for correction on the cell base IC will now be described in connection with FIGS. 13A to 13C. FIG. 13A shows an uncorrected, original circuit. In this circuit, an OR logic circuit C314 obtains an OR logic of respective outputs of logic circuits C311, C312 and C313, and applies the OR logic output to an input of a logic circuit C315. It is now assumed that this circuit should be corrected so as to apply an AND logic of the logic circuits C311, C312 and C313 to the input of the logic circuit C315 instead of the OR logic. FIG. 13C shows an example of the circuit corrected using NAND macro cells incorporated in advance. The dashed lines in the figure indicate a corrected portion. In this example, four NAND macro cells are used for correction.
In the conventional FPGA and short-term gate array, the logic circuit module M13 of FIGS. 16A and 16B is capable of representing all of two-input logic circuits, but has a larger area than that of an individually implemented two-input logic circuit. In particular, a single logic circuit module is required even if only a basic gate is necessary. This results in extremely disadvantageous area efficiency in the case of a semiconductor integrated circuit that merely requires a large number of basic gates. Thus, the resultant semiconductor integrated circuit has a large size. A semiconductor integrated circuit for digital signal processing uses a large number of adders as its circuit portion. In designing such a semiconductor integrated circuit, the adders cannot be efficiently implemented in terms of the area. Moreover, in the case of a semiconductor integrated circuit using a large number of at least three-input logic circuits, a desired semiconductor integrated circuit can be reduced in size with improved area efficiency if the at least three-input logic circuits can be implemented with a logic circuit module. In fact, however, the logic circuit module M13 can implement only a small number of types of at least three-input logic circuits. Therefore, the resultant semiconductor integrated circuit has an extremely large size.
Moreover, in the correction of a cell base IC, a portion to be corrected of a designed semiconductor circuit cannot be predicted, and NAND macro cells to be incorporated in advance must be distributed all over the semiconductor circuit. Accordingly, a long wiring length is likely to be required for partial correction, and the number of wiring layers to be modified for correction is likely to be increased. Macro cells to be incorporated in advance normally use basic gates, and therefore a large number of wiring layers are required for correction. As a result, even a slight increase in circuit scale to be corrected makes the correction difficult.
It is an object of the present invention to improve the structure of a logic circuit module so as to increase the area efficiency of the logic circuit module when implementing various logic gates in an FPGA and a short-term gate array, and thus reduce the size of the resultant semiconductor integrated circuit. It is another object of the present invention to reduce the wiring length for correction by using improved logic circuit modules as macro cells to be incorporated in advance in preparation for correction of a cell base IC. It is still another object of the present invention to reduce the number of wiring layers to be modified for correction so as to enable correction to be made in an excellent manner even if the circuit scale to be corrected is somewhat increased.
In order to achieve these objects, the present invention enables a plurality of logic functions to be represented with a single logic circuit module, and also enables a half adder to be formed with a single logic circuit module.
More specifically, a logic circuit module according to the present invention is characterized in that it comprises a plurality of input terminals, a plurality of output terminals, and a plurality of logic elements provided between the plurality of input terminals and the plurality of output terminals, the plurality of input terminals are each connected to an external signal line, a power supply or a ground so as to implement a plurality of desired logic functions, and at least two of the implemented plurality of logic functions are such that a potential state of an output terminal corresponding to one of the logic functions is not affected by a potential state of an input terminal corresponding to the other logic function.
The logic circuit module according to the present invention is characterized in that at least one of the plurality of logic elements separates at least two of the implemented plurality of logic functions from each other so as to make the two logic functions independent of each other.
A logic circuit module according to the present invention is characterized in that it comprises first to seventh input terminals, first and second output terminals, and first to third 2-1 multiplexers, the first 2-1 multiplexer has its two signal terminals respectively connected to the first and second input terminals, and its selection terminal connected to the third input terminal, the second 2-1 multiplexer has its two signal terminals respectively connected to the fourth and fifth input terminals, and its selection terminal connected to the sixth input terminal, the third 2-1 multiplexer has its two signal terminals respectively connected to signals selected by the first and second 2-1 multiplexers, and its selection terminal connected to the seventh input terminal, the first output terminal receives the signal selected by the first 2-1 multiplexer, and the second output terminal receives a signal selected by the third 2-1 multiplexer.
The logic circuit module according to the present invention is characterized in that it further comprises a two-input AND circuit, the AND circuit receives the signal selected by the first 2-1 multiplexer, the seventh input terminal is connected to the AND circuit, and the first output terminal receives an output signal of the AND circuit.
The logic circuit module according to the present invention is characterized in that the third input terminal serves also as the sixth input terminal.
The logic circuit module according to the present invention is characterized in that the first, third, fourth and sixth input terminals are respectively connected to external signal lines, and the second, fifth and seventh input terminals are connected to a power supply, thereby implementing two independent OR logics.
The logic circuit module according to the present invention is characterized in that the first and fourth input terminals are connected to a ground, the seventh input terminal is connected to a power supply, and the second, third, fifth and sixth input terminals are respectively connected to external signal lines, thereby implementing two independent AND logics.
The logic circuit module according to the present invention is characterized in that the first to sixth input terminals are respectively connected to external signal lines, and the seventh input terminal is connected to a power supply, thereby implementing two independent 2-1 multiplexer logics.
The logic circuit module according to the present invention is characterized in that the first and fifth input terminals are connected to a ground, the second and fourth input terminals are connected to a power supply, the third and sixth input terminals are connected to a common external signal line, and the seventh input terminal is connected to another external signal line so as to form an EX-OR logic and an AND logic each receiving as inputs two signals of the common external signal line and the another external signal line, thereby implementing a half adder.
A semiconductor integrated circuit according to the present invention is characterized in that it comprises four logic circuit modules each implementing the half adder, and a single logic circuit module implementing the two OR logics, and a lower-bit full adder is formed from two of the four logic circuit modules each implementing the half adder and one of the two OR logics implemented by the logic circuit module, and an upper-bit full adder is formed from the other two logic circuit modules each implementing the half adder and the other OR logic implemented by the logic circuit module, thereby implementing a 2-bit full adder.
The logic circuit module according to the present invention is characterized in that the second, fifth and sixth input terminals are respectively connected to external signal lines, the first input terminal is connected to a ground, the seventh input terminal is connected to a power supply, the third input terminal is connected to the second output terminal, and the fourth input terminal is connected to the first output terminal so as to form an AND logic and a 2-1 multiplexer that are independent of each other, and an output of the AND logic is connected to one of two signal terminals of the 2-1 multiplexer, thereby implementing a storage circuit having a reset function.
The logic circuit module according to the present invention is characterized in that the second and seventh input terminals are connected to a power supply, the first, fifth and sixth input terminals are respectively connected to external signal lines, the third input terminal is connected to the second output terminal, and the fourth input terminal is connected to the first output terminal so as to form an OR logic and a 2-1 multiplexer that are independent of each other, and an output of the OR logic is connected to a signal terminal of the 2-1 multiplexer, thereby implementing a storage circuit having a set function.
Moreover, a method for designing a semiconductor integrated circuit according to the present invention is characterized in that the semiconductor integrated circuit includes a plurality of logic circuit modules, and the semiconductor integrated circuit conducting a prescribed operation is designed by connecting the input terminals of the logic circuit modules to a power supply or ground, or connecting an input terminal of a logic circuit module to an output terminal of another logic circuit module.
The method according to the present invention is characterized by designing the semiconductor integrated circuit conducting the prescribed operation by forming in advance longitudinal and lateral wirings for connecting the input terminals of the logic circuit modules to the power supply or ground, or connecting the input terminals of the logic circuit modules to the output terminals thereof, and a plurality of connecting means for connecting the longitudinal and lateral wirings to each other, and then programming so as to connect prescribed longitudinal and lateral wirings to each other through a prescribed one of the plurality of connecting means.
A method for designing a semiconductor integrated circuit according to the present invention is characterized by manufacturing the semiconductor integrated circuit with the logic circuit module incorporated therein, and when necessity for correction of the manufactured semiconductor integrated circuit arises, correcting the semiconductor integrated circuit by connecting a wiring to the incorporated logic circuit module.
Thus, the present invention is capable of implementing at least two independent logic circuits per logic circuit module. Therefore, the area efficiency of the logic circuit module is improved over the conventional example in which only a single logic circuit is implemented per logic circuit module. Moreover, the required number of logic circuit modules is reduced, allowing for reduction in area of a wiring region provided for wirings that connect the logic circuit modules to each other. As a result, a designed semiconductor integrated circuit is reduced in size. Moreover, each logic circuit module of the present invention has a plurality of output terminals. Therefore, the logic circuit module of the present invention can represent an increased number of types of logic circuits as compared to the conventional logic circuit module having only one output terminal. For example, the logic circuit module of the present invention can represent a half adder, which cannot be represented with a single logic circuit module in the conventional example.
Moreover, according to the present invention, the logic circuit module of the present invention is incorporated in advance into the semiconductor integrated circuit for the purpose of correcting a cell base IC. Therefore, even when the necessity for correction of the manufactured semiconductor integrated circuit arises, two or more logic circuits can be integrated into a single logic circuit module, whereby the wiring length for connecting the required logic circuits to each other as well as the number of wiring layers to be modified for correction are reduced.